1. Field of the Invention
The present invention relates to a semiconductor memory technology, and in particular to a flash memory cell with split gate structure and a method for forming the same.
2. Description of the Related Art
Semiconductor memory devices are commonly available in various forms, such as EPROMs, EEPROMs, and flash memory devices. Currently, flash memory, such as a split gate flash memory is widely applied in large capacity non-volatile memory technology. Typically, the split gate flash memory includes a split gate structure having a floating gate for charge storage and a control gate to control the charge storage. The split gate structure may further include a thin gate dielectric or tunnel oxide film formed between the floating gate and the active area of a substrate and an integrate dielectric film formed between the floating gate and the control gate.
FIG. 4 shows a plan view of a conventional split gate memory array, and FIGS. 5A and 5B show cross-sections along III-III′ and IV-IV′ lines, respectively, shown in FIG. 4. The split gate memory array includes a plurality of split gate memory cells. In FIG. 5A, the split gate memory cell may further include a semiconductor substrate 400 having an active area 400a separated by shallow trench isolation (STI) structures 400b. A polysilicon floating gate 402 is disposed on the substrate 400 and insulated therefrom by a gate dielectric layer 401. A polysilicon control gate (word line) 410 is laterally adjacent to the floating gate 402 and insulated therefrom by an interpoly dielectric layer 408 and a thicker cap oxide layer 406 formed by local oxidation of silicon (LOCOS). A source region 411 and a drain region (not shown) are formed in the substrate 400 on both sides of the split gate structure.
Returning to FIGS. 4 and 5A, the floating gate 402 partially overlaps the pair of STI structures 400b. In order to avoid short circuits in neighboring cells, a sufficient spacing between neighboring floating gates 402 or between the neighboring active areas 400a is required. Thus, it is difficult to increase memory cell density due to the limitation of the larger active area 400a spacing (i.e. a space S between the neighboring active area 400a shown in FIG. 4 or 5A), and the integrated circuit performance cannot be further improved. Additionally, the source coupling ratio cannot be further improved due to the limitation of the thickness of the cap oxide layer 406. As is known in the art, the source coupling ratio of a split gate memory cell is generally used as a gauge to evaluate the programming and erasing efficiency of the cell. Increasing the source coupling ratio of the memory cell will generally result in an increase in the programming and erasing efficiency.
Thus, there exists a need in the art for development of an improved split gate memory cell which has a higher source coupling ratio while reducing the active area spacing.